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MT1328 Features

FEATURES

*Speed Performance on Servo and Decoder
- DVD-ROM up to 16XS
- CD-ROM up to 48XS
- A built-in frequency programmable clock to host interface and RSPC decoder to optimize the performance.
- A built-in DRAM interface programmable clock to optimize DRAM performance and to fit most types of DRAM.

* Channel Data Processor for the DVD-ROM and CD-ROM
- Serial interface with MT1326 RF chip.
- Small jitter analog data slicer.
- Built-in high performance data PLL for channel data demodulation.
- Jitter meter calibrates servo parameter or tune tilt servo.
- EFM/EFM+ data demodulation.
- Enhanced channel data frame sync protection.
- Enhanced the DVD-ROM sector sync protection.

* Spindle Motor Control
- Programmable frequency error gain and phase error gain.
- Varipitch speed control.

* Servo Control
- Built-in ADCs and DACs for digital servo control.
- Two general multi-level PWM/digital outputs and a general ADC input.
- Tray control output can be output as PWM or digital output.
- Built-in DSP for digital servo control including the following functions:
Programmable digital filters to cover widely ranged variation of servo characteristics
Focusing servo loop
Tracking servo loop
Sledge motor servo loop
Auto calibration after servo initialization
Shock/defect detection and protection
Unbalance detection
Actuator central servo control
- Built-in DAC interface with external actuators and a PWM interface with spindle motor driver.

* Host Interface
- Directly connected bus pins without external TTL components.
- Programmable IDE data bus driving strength.
- Licensed CSS (Content Scramble System) protection.
- Enhanced-IDE (ATAPI) host interface.
- Built-in 16-word host input data/ATAPI Packet Command FIFO.
- Build-in 16-word host output data FIFO.
- Supports ATA/ATA-2 PIO (Programmed input/output) data transfer mode and multiword-DMA data transfer mode.
- Supports ATA/ATAPI Ultra DMA transfer rate greater than 66 Mbytes/s.
- Intelligent automated target sector search.
- Hardware-macro-accelerated ATAPI command processing.
- Multi-block data transfer with automatic ATA Task File Registers handling.
- Automatic sector data transfer to Host in GPIO, DMA or UDMA mode.
- Selective transfer of sectors SYNC, Header, User Data, ECC/EDC, Error Flags, and Subcode data with automatic transfer length calculation and buffer address manipulations.
- Programmable buffer counters for buffer status tracking

* Micro controller
- 8-bit turbo 8032 high performance micro controller.
- Instruction-set compatible with MCS52
- Built-in internal 373 and 8-bit programmable lower address port.
- Additional instruction DEC DPTR
- Three 16-bit timers
- Eight three-level-prioritized interrupt sources
- Full duplex serial port
- Boolean Processor
- Programmable operating clock for high speed and sleep mode application
- 256-bytes on-chip RAM.
- 256k address space for external program memory
- Programmable Watchdog Timer
- Two 16-bit Data pointers
- High-speed Architecture.
- 4 clock/machine cycle. (Standard 8051 =12)
- Running up to 40 MHz
- Supports up to 256K bytes FLASH-programming interface.
- Supports 5/3.3-Volt. FLASH.
- Supports ICE mode.
- Supports power-down mode.
- Supports additional serial port

* CD-DA (C1/C2) Decoding Logic
- Powerful error correcting mechanism to correct quadruple errors for C1 and C2.
- Capability of ±8-frame jitter margin.
- Two individually readable 16-bit error pointer counters for C1 and C2.
- Error correction monitor signals observable through programmable I/O pins.

* CD-ROM (C3) Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA formats.
- Concurrent DSP data transfer, error correction, and host data transfer operations speed up to 48XS.
- High-speed ECC logic capable of correcting one error per P-codeword or Q-codeword.
- Automatic sector mode and Form detection.
- Automatic sector header verification.
- 8-bit counter for decodes completion check.
- Programmable descrambling and error correction schemes.
- Automatically repeated error corrections.
- Decoder Error Notification Interrupt that signals various decoder errors.

* DVD-ROM Decoding Logic
- Concurrent DSP data transfer, error correction, and host data transfer operations up to 16XS speed.
- Powerful ECC error correcting mechanism to correct 10 PI errors and 16 PO errors.
- Error correction acceleration.
- Decoder Error Notification Interrupt that signals various decoder errors
- PI error correction monitor signals output through programmable I/O pins
- 16-bit PI and PO error counter pointer that can be read by the micro controller.

* Buffer Memory Controller
- Up to 4M-word 5/3.3-Volt Fast-Page/EDO mode of DRAM buffer or 4 banks of 1M-word SDRAMs.
- Supports Fast-Page/EDO DRAMs of 8~11-bit Column Address.
- Programmable Built-in DRAM interface clock to optimize the DRAM performance.
- EDO –28 can provide the DRAM bandwidth required on 16XS DVD playing.
- Supports SDRAM interface.
- Self-refresh mode for EDO and SDRAM to reduce power consumption.
- Programmable DRAM accesses cycle and refresh cycle timing.
- Block-based sector addressing.

* Audio Processing & Built-in DAC
- Audio playback from DRAM buffer.
- Register selectable audio reference clock frequency.
- Programmable audio output format.
- IEC-958 Consumer Digital Audio output.
- Built-in digital attenuator, soft mute function, interpolator and effect circuitry.
- Separate left and right channels routing and muting controls.
- Built-in digital audio DAC including:
8-fold over-sampling digital filter
Command option digital de-emphasis filter
Built-in 2nd order switched-capacitor (SC) low pass filter
High speed audio playback

* A/V Interface
- Programmable 8-bit parallel interface compatible to popular MPEG decoder chips.
- I2S/EIAJ serial interface providing CD-ROM/CDDA data.

* Serial Interface
- H8 Serial Communication Interface.
- High-speed RS-232 asynchronous serial interface.

* Power down mode
- Whole chip power-down mode, sleep mode and standby mode.
- The micro controller, ECC Decoder, Servo DSP and partial IDE interface can be powered down individually.

* Outline
- 208-pin LQFP package

MT1326 Features

GENERAL DESCRIPTION

MT1326 is a high performance CMOS analog front-end IC for both CD_ROM driver up to 48XS and DVD-ROM driver up to 16XS. It contains servo amplifiers to generate focusing error, 3-beam tracking error, 1 beam radial push-pull signal, RF level and SBAD for servo functions. It also includes DPD tracking error signal for DVD_ROM application. Programmable equalizers and AGC circuits are also incorporated in this chip to optimize read channel performances. In addition, this chip has dual automatic laser power control circuits for DVD-ROM and CD-ROM seperately and reference voltage generators to reduce external components. Programmable functions are implemented by the access of internal register through bi-directional serial port to configure modes selection.

FEATURES

- RF equalizer with programmable from 3MHz to 70 MHz and programmable boost from 3dB to 13dB.
- Multiple configuration of RF input stages to interface various pick-up heads.
- On-line AGC.
- One beam differential phase tracking error generator for DVD_ROM application.
- Focusing error signal generator for CD-ROM, DVD-ROM.
- RF level signal generator.
- One beam differential push-pull signal generator for central servo application.
- 3 beams tracking error signal generator.
- Sub-beam added signal for 3 beams CD_ROM.
- High speed RF envelop detection circuit with bandwidth up to 400KHz for CD-ROM.
- Defect detection circuits.
- Dual automatic laser power control circuits with programmable level of LD monitor voltage.
- Vref voltage and 2Vref voltage generators.
- Bi-directional serial port to access internal registers.
- 100-pin QFP 100-pin LQFP

MT1336 Features

GENERAL DESCRIPTION

MT1336 is a high performance CMOS analog front-end IC for both CD_ROM driver up to 48XS and DVD-ROM driver up to 16XS. It also supports DVD-RAM read up to 4XS Version 2. It contains servo amplifiers to generate focusing error, 3-beam tracking error, 1 beam radial push-pull signal, RF level and SBAD for servo functions. It also includes DPD tracking error signal for DVD_ROM application. For DVD-RAM disks, there are also Differential Push-Pull (DPP) method for generating tracking signal and Differential Astigmatic Detection (DAD) for processing focusing signal. Programmable equalizer and AGC circuits are also incorporated in this chip to optimize read channel performance. In addition, this chip has dual automatic laser power control circuits for DVD-ROM (DVD-RAM) and CD-ROM seperately and reference voltage generators to reduce external components. Programmable functions are implemented by the access of internal register through bi-directional serial port to configure modes selection.

FEATURES

- RF equalizer with programmable from 3MHz to 70 MHz and programmable boost from 3dB to 13dB.
- MT1336 supports at least nine different kinds of pick-up heads with versatile input configuration for both RF input stages and servo signal blocks.
- Versatile on-line AGC.
- 3 beams tracking error signal generator for CD_ROM application.
- One beam differential phase tracking error (DPD) generator for DVD_ROM application.
- Differential push pull tracking error (DPP) generator for DVD_RAM application.
- Focusing error signal generator for CD-ROM, DVD-ROM and DVD-RAM (DAD method).
- RF level signal generator.
- Sub-beam added signal for 3 beams CD_ROM.
- One beam push-pull signal generator for central servo application.
- High speed RF envelop detection circuit with bandwidth up to 400KHz for CD-ROM.
- Defect and Blank detection circuits.
- Dual automatic laser power control circuits with programmable level of LD monitor voltage.
- Vref=1.4V voltage and V2ref=2.8V voltage generators.
- V20=2.0V voltage for pick-up head reference.
- Bi-directional serial port to access internal registers.
- 128-pin LQFP

MT1369 Features

FEATURES

* Super Integration DVD player single chip
- Servo controller and data channel processing
- MPEG-1/MPEG-2/JPEG video decoding
- AC-3/DTS/DVD-Audio audio decoding
- Unified track buffer and A/V decoding buffer
- Video processing for scaling and video quality enhancement
- OSD & Sub-picture decoding
- Built-in clock generator

* Speed Performance on Servo and Decoding
- DVD-ROM up to 8XS
- CD-ROM up to 24XS
- Built-in a frequency programmable clock to mP and RSPC Decoder to optimize the performance over power

* Channel Data Processor
- Provides interface with analog front-end processor
- Analog data slicer for small jitter capability
- Built-in high performance data PLL for channel data demodulation
- EFM/EFM+ data demodulation
- Enhanced channel data frame sync protection & DVD-ROM sector sync protection

* Servo Control and Spindle Motor Control
- Programmable frequency error gain and phase error gain of spindle PLL to control spindle motor on CLV and CAV mode
- Provide a varipitch speed control for CLV and CAV mode
- Built-in ADCs and DACs for digital servo control
- Provide 2 general PWM
- Tray control can be PWM output or digital output
- Built-in DSP for digital servo control

* Host Micro controller
- Built-in 8032 micro controller
- Built-in internal 373 and 8-bit programmable lower address port
- 256-bytes on-chip RAM
- Up to 1M bytes FLASH-programming interface
- Supports 5/3.3-Volt. FLASH interface
- Supports power-down mode
- Supports additional serial port

* DVD-ROM/CD-ROM Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA formats
- High-speed ECC logic capable of correcting one error per each P-codeword or Q-codeword
- Automatic sector Mode and Form detection
- Automatic sector Header verification
- 8-bit counter for decode completion check
- Programmable descrambling and error correction schemes
- Automatically repeated error corrections
- 8-bit C2 Pointer counter
- Decoder Error Notification Interrupt that signals various decoder errors
- Provide error correction acceleration

* Buffer Memory Controller
- Supports 16Mb/32Mb/64Mb SDRAM
- Supports 16-bit/32-bit SDRAM data bus interface
- Build in a DRAM interface programmable clock to optimize the DRAM performance
- Provide the self-refresh mode SDRAM
- Programmable DRAM access cycle and refresh cycle timings
- Block-based sector addressing
- Programmable buffering counter for buffer status tracking
- Maximum DRAM speed is 133MHz
- Support 5/3.3-Volt. DRAM Interface

* Video Decode
- Decodes MPEG1 video and MPEG2 main level, main profile video (720/480 and 720x576)
- Maximum input bit-rate of 15Mbits/sec
- Smooth digest view function with I, P and B picture decoding
- Baseline, extended-sequential and progressive JPEG image decoding
- RLE and non-RLE BMP image decoding

* Video/SPU/HLI Processor
- Arbitrary ratio vertical/horizontal scaling of video, from 0.25X to 256X
- 256/16/4/2-color bitmap format OSD
- 256/16 color RLC format OSD
- Automatic scrolling of OSD image
- Warp mode of OSD can reduce memory required
- Dual Sub-picture decoder
- Provides 4-color/32x32-pixel hardware cursor
- Fade-in, Fade out, and Wipe functions as specified in the DVD-Audio Specification and other slide show transition effects

* Audio Processing
- Decoder format supports:
Dolby Digital (AC-3) decoding
DTS decoding
MLP decoding for DVD-Audio
MPEG-1 layer 1/layer 2 audio decoding
MPEG-2 layer1/layer2 2-channel audio decoding
Dolby Pro Logic decoding
HDCD decoding
- Up to 6 channel linear PCM output for DVD Audio / DVD Video
- Downmix function
- Support IEC 60958/61937 output:
PCM / bit stream / mute mode
Custom IEC latency up to 2 frames
- Pink noise and white noise generator
- Karaoke functions:
Microphone echo with adjustable echo level, echo -depth and delay length
Microphone tone control with three custom second-order IIR filter
Vocal mute/vocal assistant
Key shift up to +/- 8 keys controlled by 1/2 key
- Channel equalizer
- 3D surround processing include virtual surround and speaker separation
- Power-down control

* Outline
- 208-pin LQFP package
- 3.3/2.5-Volt. Dual operating voltages

MT1508 Features

FEATURES

* Specification and Speed Performance
- Highly integration of servo controller, DSP, μP, ATIP decoder, spindle controller, write strategy generator, OPC/ROPC power calculator, RSPC decoder, RSPC encoder, CIRC decoder, CIRC encoder, EFM demodulator, EFM modulator, ATAPI interface controller, buffer memory manager , audio processor and flash programming controller.
- A highly automated and high-performance CD-R/RW endec/write strategy chip compatible with International Standard ISO/IEC 10149, Orange Book Part II : CD-R Version 3.1 and Orange Book Part III : CD-RW Version 2.0.
- CD-R recording up to 40XS.
- CD-RW recording up to 16XS.
- CD-ROM decoding up to 48XS.
- Clock oscillator : 33.8688MHz.

* EFM Data Processor
- Analog data slicer for small jitter capability.
- Built-in data PLL for the clock of EFM data demodulation.
- Powerful error correction. C1: quadruple correction, C2: quadruple.
- Command programmable 48XS Zone-CLV mode capability.
- Maximum outer 48XS True-CAV mode capability.
- Digital spindle servo to facilitate spindle servo control.

* Audio Processing & Built-in DAC
- IEC-958 Consumer Digital Audio output.
- Built-in digital audio DAC including

* μP Interface
- Built-in 8-bit turbo 8032 high performance micro-controllers whose pin compatible with standard 80C32 and Instruction-set compatible with MCS52.
- High speed architecture :
- 4 clock / machine cycle (standard 8051 = 12)

* Servo Control
- Built-in ADCs for digital servo control.
- Built-in DSP for digital servo control including the following functions:
- Focusing servo loop
- Tracking servo loop
- Sledge motor servo loop
- Unbalance detection
- Actuator central servo control
- Built-in DACs to interface external actuator and motor drivers.
- Less external components required for servo compensators.

* ATIP Decoding Logic
- Adaptive FM demodulator provides exact FM demodulation for wobble signal to reduce ATIP access time.
- Supports up to 40XS ATIP decoding.

* Wobble Spindle Motor Control
- Supports up to 40XS recording speed (CLV).
- Supports up to 40XS recording speed (CAV).
- Support 64 revolution count of FG.

* Write Strategy Control
- Provides signal waveform of write strategy for CD-R and CD-RW.
- Supports up to 40XS recording speed

* CD-R/RW Encoding Logic
- Supports all writing methods :
DAO (Disc At Once)
SAO (Session At Once)
TAO (Track At Once)
- Packet Writing
- Supports up to 40X recording.
- Supports Subcode P, Q, R-W encoding.
- Super-Link

* RSPC(C3) Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA formats.

* Host Interface
- Directly connected bus pins without external TTL components.
- Enhanced-IDE (ATAPI) host interface.
- Supports an ATA/ATA-2 PIO (Programmed input/output) data transfer mode and a multiword-DMA data transfer mode.
- Supports an ATA/ATAPI-4 Ultra DMA transfer mode with data rate up to 66 Mbytes/s.

* Buffer Memory Controller
§ Supports up to 4M-word 5/3.3-Volt Fast-Page/EDO mode of DRAM buffer or single 4 banks x 1M-word SDRAM or two 2 banks x 512K-word SDRAM.

* Microcontroller DMA interface
- Supports single-byte and multi-byte (max 16 bytes) access to buffer memory from microcontroller.

* Supports up to 512K bytes flash ROM.

* Built-in small jitter EFM clock synthesizer (EFMPLL) to provide preferable recording quality.

* Built-in a PLL (IPLL) circuit to provide clocks for microcontroller, host interface, buffer memory controller, encoder and the RSPC decoder.

* Power down mode
- Whole chip power-down modes support, include sleep mode and standby mode.

* Outline
- 208-pin LQFP package.

MT1516 Features

GENERAL DESCRIPTION

The MT1516 is a high performance and high integration CMOS analog front-end IC for processing the signals from CDRW pick-up head . The Chip can support CD-R Recording up to 56XS (CLV , ZCLV , CAV , PCAV mode) , CD-RW recording up to 32XS (CLV , ZCLV , CAV , PCAV mode), and CD-ROM decoding up to 56XS.

FEATURES

- Sample/hold and matrix circuit to generate the various signals required for disc decoding and recording
- Servo signal processor circuit to generate the servo control signals
- RF Equalizer with programmable cutoff frequency and programmable gain
- Wobble signal processing circuit to extract the ATIP (Absolute Time in Pre-Groove) information from CD-R/RW media
- Automatic laser power control (APC) circuits with built-in D/A converters for laser power setting
- Automatic OPC function
- High-speed peak detection and S/H circuit for running OPC (ROPC)
- Multiplexer circuit with peak/bottom detection and buffer function
- Built-in 10-Bit A/D converter for digitizing the monitor signal through the multiplexer circuit
- Built-in band-gap voltage reference circuit
- Bi-directional serial port to access the internal register setting
- With CAV-mode recording capability
- Built-in power down function
- Outline : 128 LQFP package

MT1628 Features

FEATURES

* Specification and Speed Performance
- Highly integration of servo controller, DSP, μP, ATIP decoder, spindle controller, write strategy generator, OPC/ROPC power calculator, RSPC decoder, RSPC encoder, CIRC decoder, CIRC encoder, EFM/EFM+ demodulator, EFM modulator, ATAPI interface controller, buffer memory manager , audio processor and flash programming controller.
- A highly automated and high-performance CD-R/RW endec/write strategy chip compatible with International Standard ISO/IEC 10149, Orange Book Part II : CD-R Version 3.1 and Orange Book Part III : CD-RW Version 2.0.
- CD-R recording up to 48XS.
- CD-RW recording up to 24XS.
- Support CD-ROM, CD-R/RW, DVD-ROM, DVD-R/RW, DVD-RAM, DVD+RW ver2.0 read
- CD-ROM decoding up to 48XS.
- DVD-RAM 2.6G up to 8X, 4.7G up to 4X
- DVD-ROM up to 16XS
- Support Mt. Rainier CD-RW format
- Support True-CAV, Partial-CAV and Zone-CLV recording
- Support MTK-SUPERlinka
- Clock oscillator : 33.8688MHz.

* Channel Data Processor
- Analog data slicer for small jitter capability.
- Built-in data PLL for the clock of EFM/EFM+ data demodulation.
- Powerful error correction. C1: quadruple correction, C2: quadruple.
- Command programmable 48XS Zone-CLV mode capability.
- Maximum outer 48XS True-CAV mode capability.

* Audio Processing & Built-in DAC
- Built-in digital attenuator, soft mute function, interpolator and effect circuitry.
- IEC-958 Consumer Digital Audio output.
_ Built-in digital audio DAC.

* μP Interface
- Built-in 8-bit turbo 8032 high performance micro-controllers whose pin compatible with standard 80C32 and Instruction-set compatible with MCS52.
- High speed architecture :
◎ 4 clock / machine cycle (standard 8051 = 12)
- Supports ICE mode.

* Servo Control
- Built-in ADCs for digital servo control.
- Built-in DSP for digital servo control including the following functions:
◎Focusing servo loop
◎ Tracking servo loop
- Sledge motor servo loop
◎ Actuator centrol servo control
- Built-in DACs to interface external actuator and motor drivers.

* ATIP Decoding Logic
- Adaptive FM demodulator provides exact FM demodulation for wobble signal to reduce ATIP access time.
- Supports up to 48XS ATIP decoding.

* Wobble Spindle Motor Control
- Supports up to 48XS recording speed (CLV).
- Supports up to 48XS recording speed (CAV).

* Write Strategy
- Provides signal waveform of write strategy for CD-R and CD-RW.
- Supports up to 48XS recording speed

* CD-R/RW Encoding Logic
- Supports all writing methods :
◎ DAO (Disc At Once)
◎ SAO (Session At Once)
◎ TAO (Track At Once)
◎ Packet Writing
- Supports up to 48X recording.
- Supports Subcode P, Q, R-W encoding.
- Support MTK-SUPERlinka

* RSPC(C3) Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA formats.

* DVD Decoding Logic
- Concurrent DSP data transfer, error correction, and host data transfer operations up to 16x speed.
- Powerful ECC error correcting mechanism to correct 10 PI errors and 16 PO errors.

* Defect Management Unit
- Supports defect management for DVD-RAM v1.0 and DVD-RAM v2.0.
- Support Mt. Rainier CD-RW format

* Host Interface
- Directly connected bus pins without external TTL components.
- Enhanced-IDE (ATAPI) host interface.
- Licensed CSS (Content Scramble System) protection.
- Supports an ATA/ATA-2 PIO (Programmed input/output) data transfer mode and a multiword-DMA data transfer mode.
- Supports an ATA/ATAPI Ultra DMA transfer mode with data rate greater than 100 Mbytes/s. (Ultra DMA mode 0 ~ 5)

* Buffer Memory Controller
- Supports up to 4M-word 5/3.3-Volt Fast-Page/EDO mode of DRAM buffer or single 4 banks x 1M-word SDRAM. And can also support two 2 banks x 512K-word SDRAM or support 1M-word edo DRAM.

* Microcontroller DMA interface
- Supports single-byte and multi-byte (max 16 bytes) access to buffer memory from microcontroller.

* Flash interface
- Provides 2 kinds of on-board flash programming mode :
◎Host interface programming mode.
◎Microcontroller programming mode.
- Supports up to 512K bytes flash ROM.

* Built-in small jitter EFM clock synthesizer (EFMPLL) to provide preferable recording quality.

* Built-in a PLL (IPLL) circuit to provide clocks for microcontroller, host interface, buffer memory controller, encoder and the RSPC decoder.

* Power down mode
- Whole chip power-down modes support, include sleep mode and standby mode.
- The micro controller, ECC Decoder, Servo DSP, Defect Management Unit and partial IDE interface can be powered down individually

* Outline
- 216-pin LQFP package.

MT1616 Features

GENERAL DESCRIPTION

MT1616 is a high performance CMOS analog front-end IC for CD-R recording up to 48XS, CD-RW recording up to 24XS, CD-ROM decoding up to 48XS, and DVD-ROM decoding up to 16XS. It also provides the CAV-mode recording capability and supports DVD-RAM read up to 4XS Version 2. The operational power supply voltage is 4.5V~5.5V and the system main clock is 33.8688MHz.

FEATURES

- Support different kinds of pick-up heads with versatile input configuration for both RF input and servo signal blocks
- Sample/hold and matrix circuit to generate the various signals required for disc decoding and recording
- Servo signal processor circuit to generate the servo control signals
- Differential phase tracking error (DPD) generator for DVD-ROM application
- RF Equalizer with programmable cutoff frequency and programmable gain
- Wobble signal processing circuit to extract the ATIP (Absolute Time in Pre-Groove) information from CD-R/RW media and wobble signal for DVD-RAM read
- Automatic laser power control (APC) circuits with built-in D/A converters for laser power setting
- Automatic OPC function
- High-speed peak detection and S/H circuit for running OPC (ROPC)
- Multiplexer circuit with peak/bottom detection and buffer function
- Built-in 10-Bit A/D converter for digitizing the monitor signal through the multiplexer circuit
- Built-in band-gap voltage reference circuit
- Bi-directional serial port to access the internal register setting
- With CAV-mode recording capability
- Built-in power down mode and power saving function for slim mode operation
- Outline : 128 LQFP package

MT1199 Feature

FEATURES

* RF Front End Circuit
- Working up to 56XS
- Voltage Reference Generator (V13, V26)
- Auto Laser Power Control (ALPC)
- RF signal variable gain amplifier
- CD-RW playback capability
- Focus & tracking error signal generator
- Sub beam summing signal generator
- Tracking error balance adjustable
- Actuator central servo control
- RF signal VGA function
- RF ripple detector function

* Host Interface
- Enhanced-IDE (ATAPI) host interface.
- Built-in 12-byte ATAPI Packet Command FIFO.
- Supports ATA/ATA-2 PIO (Programmed input/output) and multiword-DMA data transfer modes.
- Supports ATA/ATAPI-4 Ultra DMA transfer mode with data rate up to 66 Mbytes/s.
- Directly connected bus pins eliminating external TTL components.
- Programmable IDE data bus driving strength.
- Hardware macros accelerating ATAPI command processing.
- Multi-block data transfer with automatic ATA Task File Registers handling.
- Selective transfer of sector SYNC, Header, User Data, ECC/EDC, Error Flags, and Subcode data with automatic transfer length calculation and buffer address manipulations.
- Flash programming mode by vendor-specific ATA commands.

* RSPC Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA formats.
- Concurrent DSP data transfer, error correction, and host data transfer operations at up to 56XS speed.
- High-speed ECC logic capable of correcting one error per each P- or Q-codeword.
- Automatic sector Mode and Form detection.
- Automatic sector Header verification.
- 8-bit counter for decode completion check.
- Programmable descrambling and error correction schemes.
- Automatically repeated error corrections.
- 8-bit C2 Pointer counter.
- Decoder Error Notification Interrupt that signals various decoder errors.

* Buffer Memory Controller
- Supports up to 512Kbytes of DRAM buffer.
- Supports DRAMs of 8-bit or 9-bit Column Address.
- Supports DRAMs of 8-bit, 16-bit interleaved, or 16-bit data bus.
- Programmable DRAM access cycle and refresh cycle timings.
- Block-based sector addressing.
- Programmable Buffering Counter for buffer status tracking.

* EFM Data Processor
- Analog data slicer for small jitter capability.
- Enhanced EFM frame sync protection.
- Built-in data PLL for the clock of EFM data demodulation.
- EFM data demodulation and subcode demodulation.
- Sub-Q data CRC detection .
- Jitter free audio data gripping.

* CIRC Error Correction
- Powerful error correction. C1: quadruple correction, C2: quadruple.
- Built-in 18K (2Kx9) SRAM capability of ±8 frame jitter margin.
- Error correction monitor signals output through programmable I/O pins.

* DSP cooked data processing
- Sector SYNC detection and insertion.
- Sub-Q code registers providing the latest CRC-approved Sub-Q code data.

* Speed Operation
- Wide range of variable pitch from -66.7% to +66.7%.
- Command programmable speed select up to 22XS CLV mode capability.
- Maximum outer 56XS True-CAV mode capability.

* Spindle Motor Control
- Digital spindle servo to facilitate spindle servo control.
- Programmable digital filter for spindle servo.

* Audio Processing & Built-in DAC
- Supports audio playback from DRAM buffer.
- Register selectable audio reference clock frequency.
- Programmable audio output format.
- IEC-958 Consumer Digital Audio output.
- Built-in digital attenuator, soft mute function, interpolator and effect circuitry.
- Separate left and right channels routing and muting controls.
-Built-in digital audio DAC including:
- 8-fold oversampling digital filter
- Command option digital de-emphasis filter
- Built-in 2nd order low pass filter
- 2XS CD audio playback optional
- High speed audio playback

* mP Interface
- Built-in 8-bit turbo 8032 high performance micro-controllers whose pin compatible with standard 80C32 and Instruction-set compatible with MCS52.
- Built-in internal 373 and 8-bit programmable lower address port.
- Two 8-bit, one 6-bit and one 1-bit I/O ports.
- Three 16-bit timers.
- Eight interrupt sources with three levels of priority.
- Full duplex serial port.
- Boolean processor.
- Programmable operation clock for high speed and sleep mode application.
- 256 bytes of on-chip RAM.
- Additional internal 128 bytes for data space.
- 128K address space for external data and program memory.
- Programmable watchdog timer.
- Two 16-bit data pointers.
- High speed architecture :
- 4 clock / machine cycle (standard 8051 = 12)
- Running up to 40M Hz clock rates
- Flash programming mode by mP.

* Flash ROM Interface
- Provide 2 kinds of on-board flash programming mode :
- Host interface programming mode.
- mP programming mode.
- Support up to 128K bytes flash ROM.
- Controllable Flash read/write programming timing.

* Built-in data PLL (IPLL) circuit for various frequency clock generation to provide the usage of mP and RSPC decoder.

* Variable clock approach for data PLL control to reduce access time.

* Servo Control
- Built-in ADCs for digital servo control.
- Built-in DSP for digital servo control including the following functions:
- Programmable digital filters to cover wide range of servo characteristics
- Focusing servo loop
- Tracking servo loop
- Sledge motor servo loop
- Auto calibration after servo initialization
- Shock/defect detection and protection
- Unbalance detection
- Actuator central servo control
- Built-in DACs to interface external actuator and motor drivers.
- Less external components required for servo compensators.

* Power down mode
- Whole chip power-down modes support.
- RF,mP, RSPC Decoder and SERVO Controller can be power down individually.

* Outline
- 208-pin LQFP package.