| FEATURES |
* Specification
and Speed Performance
- Highly integration of servo controller, DSP, μP, ATIP decoder,
spindle controller, write strategy generator, OPC/ROPC power
calculator, RSPC decoder, RSPC encoder, CIRC decoder, CIRC
encoder, EFM/EFM+ demodulator, EFM modulator, ATAPI interface
controller, buffer memory manager , audio processor and flash
programming controller.
- A highly automated and high-performance CD-R/RW endec/write
strategy chip compatible with International Standard ISO/IEC
10149, Orange Book Part II : CD-R Version 3.1 and Orange Book
Part III : CD-RW Version 2.0.
- CD-R recording up to 48XS.
- CD-RW recording up to 24XS.
- Support CD-ROM, CD-R/RW, DVD-ROM, DVD-R/RW, DVD-RAM, DVD+RW
ver2.0 read
- CD-ROM decoding up to 48XS.
- DVD-RAM 2.6G up to 8X, 4.7G up to 4X
- DVD-ROM up to 16XS
- Support Mt. Rainier CD-RW format
- Support True-CAV, Partial-CAV and Zone-CLV recording
- Support MTK-SUPERlinka
- Clock oscillator : 33.8688MHz.
* Channel Data Processor
- Analog data slicer for small jitter capability.
- Built-in data PLL for the clock of EFM/EFM+ data demodulation.
- Powerful error correction. C1: quadruple correction, C2:
quadruple.
- Command programmable 48XS Zone-CLV mode capability.
- Maximum outer 48XS True-CAV mode capability.
* Audio Processing & Built-in DAC
- Built-in digital attenuator, soft mute function, interpolator
and effect circuitry.
- IEC-958 Consumer Digital Audio output.
_ Built-in digital audio DAC.
* μP Interface
- Built-in 8-bit turbo 8032 high performance micro-controllers
whose pin compatible with standard 80C32 and Instruction-set
compatible with MCS52.
- High speed architecture :
◎ 4 clock / machine cycle (standard 8051 = 12)
- Supports ICE mode.
* Servo Control
- Built-in ADCs for digital servo control.
- Built-in DSP for digital servo control including the following
functions:
◎Focusing servo loop
◎ Tracking servo loop
- Sledge motor servo loop
◎ Actuator centrol servo control
- Built-in DACs to interface external actuator and motor drivers.
* ATIP Decoding Logic
- Adaptive FM demodulator provides exact FM demodulation for
wobble signal to reduce ATIP access time.
- Supports up to 48XS ATIP decoding.
* Wobble Spindle Motor Control
- Supports up to 48XS recording speed (CLV).
- Supports up to 48XS recording speed (CAV).
* Write Strategy
- Provides signal waveform of write strategy for CD-R and
CD-RW.
- Supports up to 48XS recording speed
* CD-R/RW Encoding Logic
- Supports all writing methods :
◎ DAO (Disc At Once)
◎ SAO (Session At Once)
◎ TAO (Track At Once)
◎ Packet Writing
- Supports up to 48X recording.
- Supports Subcode P, Q, R-W encoding.
- Support MTK-SUPERlinka
* RSPC(C3) Decoding Logic
- Supports CD-ROM Mode 1, CD-ROM XA Mode 2 Form 1, CD-ROM
XA Mode 2 Form 2, and CD-DA formats.
* DVD Decoding Logic
- Concurrent DSP data transfer, error correction, and host
data transfer operations up to 16x speed.
- Powerful ECC error correcting mechanism to correct 10 PI
errors and 16 PO errors.
* Defect Management Unit
- Supports defect management for DVD-RAM v1.0 and DVD-RAM
v2.0.
- Support Mt. Rainier CD-RW format
* Host Interface
- Directly connected bus pins without external TTL components.
- Enhanced-IDE (ATAPI) host interface.
- Licensed CSS (Content Scramble System) protection.
- Supports an ATA/ATA-2 PIO (Programmed input/output) data
transfer mode and a multiword-DMA data transfer mode.
- Supports an ATA/ATAPI Ultra DMA transfer mode with data
rate greater than 100 Mbytes/s. (Ultra DMA mode 0 ~ 5)
* Buffer Memory Controller
- Supports up to 4M-word 5/3.3-Volt Fast-Page/EDO mode of
DRAM buffer or single 4 banks x 1M-word SDRAM. And can also
support two 2 banks x 512K-word SDRAM or support 1M-word edo
DRAM.
* Microcontroller DMA interface
- Supports single-byte and multi-byte (max 16 bytes) access
to buffer memory from microcontroller.
* Flash interface
- Provides 2 kinds of on-board flash programming mode :
◎Host interface programming mode.
◎Microcontroller programming mode.
- Supports up to 512K bytes flash ROM.
* Built-in small jitter EFM clock synthesizer (EFMPLL) to
provide preferable recording quality.
* Built-in a PLL (IPLL) circuit to provide clocks for microcontroller,
host interface, buffer memory controller, encoder and the
RSPC decoder.
* Power down mode
- Whole chip power-down modes support, include sleep mode
and standby mode.
- The micro controller, ECC Decoder, Servo DSP, Defect Management
Unit and partial IDE interface can be powered down individually
* Outline
- 216-pin LQFP package. |
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